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12th May 2019, 17:02 #1
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VHDL modulo 2^64 addition
I'm working on SHA512 VHDL implementation and i need to perform (addition mod 2^64)
How can i make the following addition as (modulo 2^64 addition)
Code:a(i) <= std_logic_vector(unsigned(h(i1)) +unsigned(f3(i)) + unsigned(f0(i)) +unsigned(k(i)) + unsigned(w(i)) + unsigned(f2(i)) + unsigned(f1(i)));

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12th May 2019, 18:40 #2
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Re: VHDL modulo 2^64 addition
make a(i) 64 bits.
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12th May 2019, 19:41 #3
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12th May 2019, 20:05 #4
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Re: VHDL modulo 2^64 addition
Hi,
I noticed that you used this: std_logic_vector(unsigned(h(i1))
Why not try this: std_logic_vector(unsigned(h(i)1)
I don't quite understand what you're doing though but if you show your code, then I can follow.
Akanimo.
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12th May 2019, 22:03 #5
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Re: VHDL modulo 2^64 addition
Hi,
Signed or unsigned values?
KlausPlease don´t contact me via PM, because there is no time to respond to them. No friend requests. Thank you.

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13th May 2019, 05:17 #6
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13th May 2019, 16:58 #7

13th May 2019, 18:39 #8
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Re: VHDL modulo 2^64 addition
Hi,
Since every quantity in the equation is specified as unsigned, then surely it's unsigned ?
KlausPlease don´t contact me via PM, because there is no time to respond to them. No friend requests. Thank you.

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13th May 2019, 21:23 #9
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Re: VHDL modulo 2^64 addition
Also, I did not understand the symbol " <= ". Is this a qualifier equation or is it an inequality ??
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14th May 2019, 12:42 #10
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14th May 2019, 17:08 #11
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Re: VHDL modulo 2^64 addition
The code shown looks correct for this problem. My guess is that one or more of the terms is incorrect.
For any encryption core, you really need to get detailed test vectors. Not just input and final output, but all intermediate terms for every iteration. when everything looks random by design it is harder to intuitively trace the problem to a source.
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